The present invention relates to a semiconductor device such as a level shifter circuit or the like, which has a plurality of power supply systems and includes circuits having a configuration wherein a signal outputted from the circuit which belongs to one power supply system is received as a signal inputted to each of the circuits which belong to different power supply systems, and specifically to a semiconductor device using transistors as circuit constituent transistors, each of which adopts a so-called salicide structure wherein a compound layer (hereinafter described as salicide layer) of silicon and a metal is formed on the surface of an impurity diffusion layer to reduce a parasitic resistance of the impurity diffusion layer.
A semiconductor device having a plurality of power supply systems has been in the mainstream in recent years. For instance, a driver LSI (Large Scale Integrated Circuit) for driving various display units has such a configuration that a control system is driven by a low voltage (e.g., 3V) to reduce power consumption, and a high voltage of a few 10V is supplied as a voltage to be outputted to the corresponding display unit to thereby protect display quality (contrast). Even a semiconductor device generally called a system LSI takes such a configuration that a logical circuit is driven by a low voltage (e.g., 3V) and a necessary voltage (e.g., 5V) can be supplied to a semiconductor device to be controlled as an output voltage. This type of semiconductor device has a plurality of power supply systems and includes circuits having such a configuration that a signal outputted from the circuit that belongs to one power supply system is received as a signal to be inputted to each of the circuits that belong to the different power supply systems.
Such a semiconductor device (for example, a semiconductor device such as a level shifter circuit or the like, including circuits having such a configuration that a signal outputted from the circuit that belongs to one power supply system is received as a signal inputted to each of the circuits that belong to different power supply systems) having the plurality of power supply systems is also normally provided with a protection circuit to protect operation circuits from electrostatic discharge (ESD) or the like.
As a protection transistor constituting the present protection circuit, a transistor having a structure, a so-called salicide structure, wherein a clock frequency of a device is made fast and a salicide layer is formed on a source/drain so as to suppress a parasitic resistance as low as possible has been in the mainstream in recent years. However, a problem arises in that the transistor having such a salicide structure is low in resistance and easily destructed or damaged by an electrostatic surge. With a view toward to increasing the resistance of the protection transistor to avoid its easy damage due to the electrostatic surge, a method of fabricating a transistor having such a structure that a silicide layer low in resistance is not formed selectively, as a transistor constituting a protection circuit, has therefore been disclosed in, for example, U.S. Pat. No. 5,021,853. Further, a transistor such a configuration that a high-resistance TixNySi layer (mixing layer) is provided, has been disclosed in Japanese Patent Publication No. Hei 9(1997)-023005.
However, the use of the protection circuit comprised of the protection transistor increased in resistance means that an electrostatic surge voltage entered through a source or power supply becomes apt to be transferred to each operation circuit, whereas an electrostatic surge becomes hard to be transferred to the protection circuit. This shows that the protection circuit which has heretofore been effective, has no practical applicability.
The present invention may provide a semiconductor device having power supply systems, which prevents electrostatic surge-based breakdown or damage of a gate oxide film for each interface transistor of circuits having such a configuration that a signal outputted from the circuit that belongs to one power supply system is received as a signal to be inputted to each of the circuits that belong to different power supply systems.
According to the present invention, there is provided a semiconductor circuit has an output circuit, an input circuit and an input protection circuit. The output circuit is connected to a first power supplying terminal and a reference terminal for outputting an output signal. The output circuit has first transistors serially connected between the first terminal and the reference terminal. The input circuit is connected to a second power supplying terminal and the reference terminal. The input circuit has second transistors serially connected between the second terminal and the reference terminal. Each of the first and second transistors has a gate, a source and a drain. In the source and drain, there is a first low resistance region around a contact formed thereon so that a high resistance region is located between the gate and the first low resistance region.